1. Field of the Invention
The present invention relates to microprocessors, and more particularly to a method for managing the stack of a microprocessor for saving contextual data upon a switch from a first to a second program. The present invention aims in particular to produce a microprocessor with extended memory array that is compatible with a microprocessor with reduced memory array.
2. Description of the Related Art
FIG. 1 very schematically represents a prior art first generation 8-bit microprocessor MP1 marketed by the applicant. The microprocessor comprises a central processing unit or CPU and a memory array MEM1 addressable through a 16-bit address bus ADBUS and accessible through an 8-bit data bus DBUS. The memory array thus has a maximum size of 64 Kbytes (216 bytes) and comprises various memory zones among which particularly a volatile memory zone DMEM, for saving application data, a volatile memory zone forming a stack STK, as well as a non-volatile program memory zone PRGMEM for saving one or more application programs can be distinguished. The volatile memory zones are for example of RAM type and the non-volatile memory zones of ROM, EPROM, EEPROM or Flash type.
The CPU comprises various registers of 8 bits in which contextual data CTX are stored. A condition code register CCR, an accumulator ACC, an index register X, and registers PCL, PCH respectively receiving the least significant byte and the most significant byte of a program counter PC can be distinguished. During the execution of a program, the program counter PC designates the address of the next instruction to be executed and is incremented after reading the previous instruction. The index register X contains data required to execute instructions with indexed addressing or operations provided by an application program. The accumulator ACC contains the result of calculations or operations performed by the arithmetic and logic unit of the CPU (not represented).
As represented in FIG. 1A, the register CCR contains flags indicating results of operations or of instructions, typically the flags C (Carry), Z (Zero), N (Negative), H (Half Carry), IO and I1 (interrupt masks) and here contains two unused locations (two bits).
When the CPU switches from a program in course of execution to another program, generally an interrupt subprogram, the CPU saves the contextual data CTX present in the registers CCR, ACC, X, PCH, PCL in the stack STK then reads the address of the first instruction of the subprogram at a location of the program memory PRGMEM designated by an interrupt vector, loads this new address into the program counter PC, the initial content of which has been saved in the stack, and executes the subprogram.
The contextual data CTX are saved byte by byte in the stack STK, from a bottom address ADL and up to a top address ADH that are invariable and fixed by the manufacturer. The save address of the contextual data is indicated by a stack pointer SP stored in registers SPL, SPH of the CPU, these registers respectively containing the least significant byte and the most significant byte of the stack pointer. After each save of a byte of contextual data, the stack pointer is incremented by one unit.
The size of the stack and the number of bytes of contextual data to be saved upon each switch from one program to another, determine the number of switches into interleaved programs that can be performed by the CPU, i.e., the number of latency interrupts that can be handled successively and cumulatively. If the contextual data comprise five bytes as indicated above, and if the stack extends for example over 25 lines of the memory array MEM1, the CPU can perform 25/5, i.e., 5 cascade switches without the stack overflowing. Therefore stacked contextual data CTX1, CTX2, CTX3, . . . CTXj as represented in FIG. 1 are found in the stack.
Upon each return to an initial program (that may be an interrupt subprogram in the case of interleaved subprograms) the contextual data stored in the stack STK are recovered by the CPU at the location indicated by the stack pointer SP, the state of the registers CCR, ACC, X, PCH, PCL is restored and the CPU resumes the execution of the initial program at the place at which it had been interrupted. Upon each restoration of a byte of contextual data, the stack pointer is decremented by one unit, according to the LIFO (“Last In First Out”) pushing/popping principle in which the last datum entered is the first datum read.
FIG. 2 schematically represents a new generation 8-bit microprocessor MP2, intended by the applicant. The microprocessor MP2 differs from the microprocessor MP1 by the fact that it comprises an extended memory array MEM2 addressable under 24 bits instead of 16 bits, via the address bus ADBUS. Therefore, the memory array MEM2 here comprises 256 sectors SCT0, SCT1, . . . SCT255 of 64 KB each, and the first sector SCT0 corresponds to the memory array MEM1 of the microprocessor MP1.
This extension of the memory array requires providing an additional register PCE (“Program Counter Extended Address”) in the CPU, for obtaining a program counter PC of 24 bits instead of 16, adapted to the size of the extended memory array.
Upon each switch from a first to a second program, the CPU must therefore save the content of the six registers CCR, ACC, X, PCE, PCH, PCL in the stack STK, i.e., six bytes of contextual data CTX instead of five.
It is desirable for the microprocessor MP2 to be compatible with the microprocessor MP1, that is that it can receive and execute application programs developed for the microprocessor MP1. The space allocated to the stack STK must therefore remain constant and remain delimited by the addresses ADL, ADH in the sector SCT0. If this is not the case, if a change in the size and/or in the location of the stack of the microprocessor were provided, this change could lead to an encroachment of the program data and of the application data of the program designed for the microprocessor MP1, on the location of the stack of the microprocessor MP2.
However, the following problem arises: as the size of the stack STK is kept constant, providing the extended addressing register PCE limits the number of programs that can be interleaved since one additional byte of contextual data must be saved. By referring again to the example of a stack comprising 25 save locations, the number of programs that can be interleaved is now 25/6, i.e., 4 instead of 5 (one line of the stack STK remaining unused).
This constitutes an obstacle to the desired compatibility, as a program developed for the former generation of microprocessors could use the resources of the stack to the maximum. The execution of this program will result in the occurrence of a failure since the CPU will not be able to increment the stack pointer above the address ADH, such that contextual data will be lost.